Digital-to-analog conversion circuit and method, source driver and display apparatus

ABSTRACT

Embodiments of the present disclosure relate to a digital-to-analog conversion circuit and method, a source driver, and a display apparatus. The digital-to-analog conversion circuit includes a first digital-to-analog converter corresponding to m high bits of (m+n)-bit digital signal and a second digital-to-analog converter corresponding to n low bits, where m and n are integers greater than 0. The first digital-to-analog converter comprises a voltage division module configured to generate 2m reference voltages at equal intervals in voltage; a first voltage selection module configured to select, from the 2m reference voltages, a first voltage corresponding to the m bits; and an operation module configured to generate a second voltage higher than the first voltage by the interval in voltage based on two adjacent reference voltages of the 2m reference voltages and the first voltage. The second digital-to-analog converter is configured to generate a third voltage corresponding to the n bits by using the first voltage and the second voltage as reference voltages, and to generate the sum of the third voltage and the first voltage.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is a U.S. National Phase Application of PCTInternational Application No. PCT/CN2017/092147, filed on Jul. 7, 2017,entitled “Digital-to-Analog Conversion Circuit and Method, Source Driverand Display Apparatus”, which claims priority to the Chinese PatentApplication No. 201710017045.3, filed on Jan. 10, 2017, and thedisclosure of the above PCT International Application and the ChinesePatent Application are incorporated herein by reference in its entirety.

TECHNICAL FIELD

Embodiments of the present disclosure relate to the field of electroniccircuits, and more particularly, to digital-to-analog conversioncircuits and methods, source drivers and display apparatuses.

BACKGROUND

Organic Light-Emitting Diodes (OLEDs) as a type of current-typelight-emitting elements have become the mainstream display elements ofthe current display device, because of its thin, fast response, highcontrast and other characteristics. OLED can be classified into thepassive matrix driven OLED (PMOLED) and the active matrix driven OLED(AMOLED) according to driving methods. AMOLED has advantages such asshort driving time, low power consumption, wide viewing angle, etc., andthus is applied to television, tablet and other device increasingly.

With the development of high-definition display technology, requirementsto digital-to-analog conversion (DAC) performance in video processorsare also getting higher and higher, usually requiring more than 10 bits.The current structure of the video processing DAC mainly includes acurrent steering and a resistor string voltage division type.Conventional current steering has characteristics such as high speed,high precision and so on. However, when the current steering is used todrive video transmission, the DAC output impedance must be equal to thecharacteristic impedance of the transmission line in order to suppresssignal reflection. That is, the source current is twice that of thesignal circuit, introducing higher power consumption. The resistorstring voltage division type has advantages such as simple structure,small glitches and good linearity. However, the accuracy of the resistorvoltage division type is mainly determined by the matching of theresistor string. In a general digital process, the resistor voltagedivision type can only reach about 8 bits.

For a general large-size AMOLED source driver, there are hundreds oreven thousands of DACs per column driver circuit. Thus, the area of theDACs greatly affects the area of the entire driver chip, and the totalarea occupied by the DACs on the entire chip is usually as high as60%-70%. Therefore, it is desirable to optimize the DAC structure andreduce the switch area while ensuring accuracy.

SUMMARY

In order to at least partially solve or alleviate the above problems,the embodiments of the present disclosure provide a digital-to-analogconversion circuit and method, a source driver and a display apparatus.

According to an aspect of the present disclosure, there is provided adigital-to-analog conversion circuit, comprising a firstdigital-to-analog converter corresponding to m high bits of (m+n)-bitdigital signal and a second digital-to-analog converter corresponding ton low bits, m and n being integers greater than 0. The firstdigital-to-analog converter comprises a voltage division moduleconfigured to generate 2^(m) reference voltages at equal interval involtage; a first voltage selection module configured to select a firstvoltage corresponding to the m bits from the 2^(m) reference voltages;and an operation module configured to generate a second voltage higherthan the first voltage by the interval in voltage from two adjacentreference voltages of the 2^(m) reference voltages and the firstvoltage. The second digital-to-analog converter is configured togenerate a third voltage corresponding to the n bits by using the firstvoltage and the second voltage as reference voltages, and generate thesum of the third voltage and the first voltage.

In an embodiment of the present disclosure, the operation modulecomprises a first operation amplifier. The first operation amplifierincludes a first non-inverting input terminal configured to receive thefirst voltage; a second non-inverting input terminal configured toreceive the higher one of the two adjacent reference voltages; a firstinverting input terminal configured to receive the lower one of the twoadjacent reference voltages; a second inverting input terminal coupledto the output terminal; and the output terminal configured to output thesecond voltage.

In an embodiment of the present disclosure, the two adjacent referencevoltages are in the middle of the 2^(m) reference voltages.

In an embodiment of the present disclosure, the first voltage selectionmodule comprises a binary switch tree including m layers, the firstlayer including two switch branches coupled to the output terminal, them^(th) layer including 2^(m) switch branches respectively coupled to oneof the 2^(m) reference voltages, and each of the m layers beingcontrolled by one of the m bits, so that the output terminal outputs thefirst voltage. Wherein switching elements of the switch branchescorresponding to the reference voltages higher than or equal to apredetermined voltage among the 2^(m) reference voltages are P-typetransistors, and switching elements of the switch branches correspondingto the reference voltages lower than the predetermined voltage among the2^(m) reference voltages are N-type transistors.

In an embodiment of the present disclosure, the predetermined voltage isin the middle of the 2^(m) reference voltages.

In an embodiment of the present disclosure, the second digital-to-analogconverter comprises n second voltage selection modules each of which isconfigured to select the first voltage or the second voltage accordingto one of the n bits; and a weighted summing module configured togenerate the third voltage as a weighted sum of the output voltages ofthe n second voltage selection modules and to generate the sum of thethird voltage and the first voltage.

In an embodiment of the present disclosure, the second voltage selectionmodules are transmission gates; the weighted summing module comprises asecond operation amplifier including first to n^(th) non-inverting inputterminals configured to receive the output voltages of the n secondvoltage selection modules; a (n+1)^(th) non-inverting input terminalconfigured to receive the first voltage; an inverting input terminalcoupled to the output terminal; and the output terminal configured tooutput the sum of the third voltage and the first voltage.

In an embodiment of the present disclosure, the voltage division moduleis a resistor string type voltage division module.

According to another aspect of the present disclosure, there is provideda source driver including the above digital-to-analog conversioncircuit.

According to another aspect of the present disclosure, there is provideda display apparatus including the above source driver.

According to another aspect of the present disclosure, there is provideda method for digital-to-analog conversion including performing a firstdigital-to-analog conversion corresponding to m high bits of (m+n)-bitdigital signal and a second digital-to-analog conversion correspondingto n low bits, m and n being integers greater than 0. The performing ofthe first digital-to-analog conversion comprises generating 2^(m)reference voltages at equal intervals in voltage, selecting a firstvoltage corresponding to the m bits from the 2^(m) reference voltages,and generating a second voltage higher than the first voltage by theinterval in voltage from two adjacent reference voltages of the 2^(m)reference voltages and the first voltage. The performing of the seconddigital-to-analog conversion comprises generating a third voltagecorresponding to the n bits by using the first voltage and the secondvoltage as reference voltages, and generating the sum of the thirdvoltage and the first voltage.

In an embodiment of the present disclosure, the first voltage isselected using a binary switch tree, and the binary switch tree includesm layers, the first layer including two switch branches coupled to theoutput terminal, the m^(th) layer including 2^(m) switch branchesrespectively coupled to one of the 2^(m) reference voltages, and each ofthe m layers being controlled by one of the m bits, so that the outputterminal outputs the first voltage. Wherein switching elements of theswitch branches corresponding to the reference voltages higher than orequal to a predetermined voltage among the 2^(m) reference voltages areP-type transistors, and switching elements of the switch branchescorresponding to the reference voltages lower than the predeterminedvoltage among the 2^(m) reference voltages are N-type transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of theembodiments of the present disclosure, the accompanying drawings of theembodiments will be briefly described below. It is to be understood thatthe accompanying drawings described below are merely some embodiments ofthe present disclosure and are not intended to be limiting of thepresent disclosure, wherein in the accompanying drawings:

FIG. 1 is a schematic block diagram of a digital-to-analog conversioncircuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram for illustrating thedigital-to-analog conversion circuit of FIG. 1;

FIG. 3 is a circuit diagram of a first voltage selection moduleaccording to one embodiment of the present disclosure;

FIG. 4 is a circuit diagram of an operation module according to oneembodiment of the present disclosure;

FIG. 5 is a flowchart of a method for digital-to-analog conversionaccording to an embodiment of the present disclosure; and

FIG. 6 is a schematic block diagram of a display apparatus according toan embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to enable the purposes, technical solutions and advantages ofthe embodiments of the present disclosure to be clearer, the technicalsolutions according to the embodiments of the present disclosure will bedescribed clearly and completely in conjunction with the accompanyingdrawings. Obviously, the described embodiments are merely a part of theembodiments of the present disclosure, instead of all the embodiments.All other embodiments obtained by one of ordinary skill in the art basedon the described embodiments without contributing any creative labor arealso within the scope of the present disclosure.

In the following, unless otherwise specified, an expression “an elementA is coupled to an element B” means that the element A is connected tothe element B “directly” or “indirectly” via one or more other elements.

As previously described, the embodiments of the present disclosureprovide a digital-to-analog conversion circuit and method, a sourcedriver and a display apparatus, which can optimize the DAC structure andeffectively reduce the switching area while ensuring accuracy, therebyreducing the chip area. In the following, the digital-to-analogconversion circuit and method, the source driver and the displayapparatus according to the present disclosure will be described indetail with corresponding embodiments.

I. Digital-To-Analog Conversion Circuit

FIG. 1 is a schematic block diagram of a digital-to-analog conversioncircuit according to an embodiment of the present disclosure. Thedigital-to-analog conversion circuit can convert a (m+n)-bit digitalsignal into a corresponding analog signal, wherein m and n are integersgreater than 0. As illustrated, the digital-to-analog conversion circuitmay include a first digital-to-analog converter 110 and a seconddigital-to-analog converter 120. The first digital-to-analog converter110 can convert m bits in high bits of the digital signal, and include avoltage division module 112, a first voltage selection module 114 and anoperation module 116. The second digital-to-analog converter 120 canconvert n bits in low bits of the digital signal.

In the first digital-to-analog converter 110, the voltage divisionmodule 112 may be configured to generate 2^(m) reference voltages atequal intervals in voltage. The first voltage selection module 114 maybe configured to select a first voltage corresponding to m high bitsfrom the 2^(m) reference voltages. The operation module 116 may beconfigured to generate a second voltage higher than the first voltage bythe interval in voltage according to two adjacent reference voltages ofthe 2^(m) reference voltages and the first voltage.

The second digital-to-analog converter 120 may be configured to generatea third voltage corresponding to n low bits by using the first voltageand the second voltage as reference voltages, and generate a sum of thethird voltage and the first voltage. Since the first voltage correspondsto m bits in high bits and the third voltage corresponds to n low bits,the sum of the third voltage and the first voltage output by the seconddigital-to-analog converter 120 may be analog signal corresponding tothe (m+n)-bit digital signal.

According to the above embodiment, two digital-to-analog converters areused, and at least the first digital-to-analog converter correspondingto m bits is the voltage division type, thereby reducing the number ofswitches required for voltage selection as compared with directly usinga single (m+n)-bit voltage division type digital-to-analog converter. Inaddition, in the first digital-to-analog converter corresponding to mhigh bits which mainly affects the digital-to-analog conversionperformance, the adjacent voltage of the first voltage, that is, thesecond voltage, can be obtained only by the operation module. Thus, ascompared with conventional digital-to-analog conversion circuits whichobtain the adjacent voltage by using binary switch tree, the number ofswitches required to obtain the adjacent voltage can be reducedsignificantly.

FIG. 2 is a schematic circuit diagram for illustrating thedigital-to-analog conversion circuit of FIG. 1. In this example, m is 7and n is 3. Thus, the digital-to-analog conversion circuit in FIG. 2 canconvert a 10-bit digital signal (D9D8 . . . D1D0) into a correspondinganalog signal. As illustrated in FIG. 2, the digital-to-analogconversion circuit may include a first digital-to-analog converter 210and a second digital-to-analog converter 220, corresponding to FIG. 1.The first digital-to-analog converter 210 can convert 7-bit digitalsignal (D9D8 . . . D4D3) in high bits, and include a voltage divisionmodule 212, a first voltage selection module 214 and an operation module216. The second digital-to-analog converter 220 can convert 3-bitdigital signal (D2D1D0) in low bits.

In this example, the voltage division module 212 has the resistor stringtype voltage division structure which includes 127 (that is, 2⁷−1)resistors R0-R126 connected in series with the same resistances, whereinR0 is grounded and R126 is connected to a reference voltage. As such,128 reference voltages at equal intervals in voltage may be generated atrespective terminals of the respective resistors. The 128 referencevoltages may be marked with V0, V1, . . . , V127 respectively, in theorder of the voltage value from low to high. However, the presentdisclosure is not limited to this configuration. In other embodiments,R126 may be grounded and R0 may be connected to a reference voltage, and128 reference voltages at equal intervals in voltage may be output inthe order of the voltage value from high to low. In this case, thecircuit connection relationship of the downstream modules may beadjusted accordingly, thereby achieving the same function.

The first voltage selection module 214 may have a binary switch treestructure. FIG. 3 illustrates a schematic circuit diagram of the firstvoltage selection module 214 according to one embodiment of the presentdisclosure. As illustrated in FIG. 3, the binary switch tree has 7layers. The first layer includes 2 (i.e., 2¹) switch branches coupled tothe output terminal, and the seventh layer includes 128 (i.e., 2⁷)switch branches respectively coupled to the 128 reference voltages. Inaddition, the i^(th) layer (1<i<7) includes 2^(i) switch branches, andis coupled between the (i+1)^(th) layer and the (i−1)^(th) layeraccordingly. In each layer, each two adjacent switch branches arecoupled together. Each of the 7 layers is controlled by one of the 7bits, so that one of each two adjacent switch branches is switched on inorder to select corresponding reference voltage. As such, from 128reference voltages, through layer-by-layer selection, the outputterminal outputs the first voltage VL corresponding to the 7 high bits(D9D8 . . . D3).

In each switch branch, a single transistor may be used as a switchingelement including N-type transistors or P-type transistors. Optionally,the transistor may be N-type or P-type field effect transistor (MOSFET)of which the gate is referred to as control electrode. Since the sourceand the drain of the transistor are symmetrical, there is nodistinguishing between the source and the drain. That is, the source ofthe transistor may be the first electrode (or the second electrode), andthe drain may be the second electrode (or the first electrode).Optionally, it is also possible to implement the function of the singletransistor using any controlled switching device (e.g., CMOStransmission gate) with a strobe signal input. A controlled middleterminal of the controlled switching device receiving a control signal(e.g., for switching on or switching off the switching device) isreferred to as a control electrode, and the other two terminals are afirst electrode and a second electrode respectively.

In the example of FIG. 3, a single transistor is used as the switchingelement. The switching elements of the switch branches corresponding tohigh voltages higher than or equal to a predetermined voltage from amongthe 128 reference voltages may be provided as P-type transistors, andthe switching elements of the switch branches corresponding to lowvoltages lower than the predetermined voltage from among the 128reference voltages may be provided as N-type transistors. Thepredetermined voltage for distinguishing the high voltages from the lowvoltages may be the median of the 128 reference voltages. Specifically,the reference voltages higher than or equal to V64 are high voltages,and the reference voltages lower than V64 are low voltages. It should benoted that the predetermined voltage is not limited to the median of the128 reference voltages, as long as it is in the middle range.

In an embodiment of the present disclosure, since a single transistor isused as the switching element to transmit voltages (e.g., grayscalevalues of the image signal), the number of switches can be reduced,thereby reducing the chip area and the production cost. Further, thecharacteristics of the P-type transistor transmitting stable highvoltages and N-type transistor transmitting stable low voltages arebased on. For example, in the embodiment of the present disclosure, aP-type transistor is used to transmit a high grayscale and an N-typetransistor is used to transmit a low grayscale so as to ensure a stabletransmission over a full range.

A structure of a 7-layer binary switch tree according to an embodimentof the present disclosure will be described in detail below. The 7^(th)layer of the binary switch tree may include 64 N-type transistorsM7,0-M7,63 and 64 P-type transistors M7,64-M7,127. The first electrodesof the respective transistors may be coupled to the reference voltagesV0-V127 accordingly. For example, the first electrode of the transistorM7,0 is coupled to V0, and the first electrode of the transistor M7,64is coupled to V64. The control electrode of each transistor may beaccordingly coupled to the 4^(th) digit D3 of the digital signal and itscomplementary digit D3′. In particular, the control electrodes of therespective N-type transistors are coupled to the digits D3 and D3′ atintervals, and the control electrodes of the respective P-typetransistors are coupled to the digits D3 and D3′ at intervals. Forexample, the control electrode of M7,0 is coupled to D3′, and thecontrol electrode of M7,1 is coupled to D3. D3 and D3′ are complementarysignals. For example, if D3 is 1, D3′ is 0; and if D3 is 0, D3′ is 1.

The 6^(th) layer of the binary switch tree may include 32 N-typetransistors M6,0-M6,31 and 32 P-type transistors M6,32-M6,63. The firstelectrodes of the respective transistors may be coupled to the secondelectrodes of two adjacent transistors in the 7^(th) layer accordingly.For example, the first electrode of the transistor M6,0 is coupled tothe second electrode of the transistor M7,0 and the second electrode ofthe transistor M7,1. The control electrode of each transistor may beaccordingly coupled to the 5^(th) digit D4 of the digital signal and itscomplementary digit D4′. In particular, the control electrodes of therespective N-type transistors are coupled to the digits D4 and D4′ atintervals, and the control electrodes of the respective P-typetransistors are coupled to the digits D4 and D4′ at intervals. Forexample, the control electrode of M6,0 is coupled to D4′, and thecontrol electrode of M6,1 is coupled to D4. The configurations of layer5 to layer 2 of the binary switch tree are similar to the aboveconfiguration, and thus will not be described again.

The first layer of the binary switch tree may include one N-typetransistor M1,0 and one P-type transistor M1,1. Similarly, the firstelectrode of the transistor M1,0 may be coupled to the second electrodesof two N-type transistors in the second layer, and the first electrodeof the transistor M1,1 may be coupled to the second electrodes of twoP-type transistors in the second layer. Each of the control electrodesof the transistors M1,0 and M1,1 may be coupled to the complementarydigit D9′ of the 10^(th) digit D9 of the digital signal, and the secondelectrodes may be coupled together to form the output terminal of thebinary switch tree. After the voltage is transmitted layer by layer, thecorresponding first voltage VL is output.

In addition, in other embodiments using 128 reference voltages from highto low, N-type transistors and P-type transistors in the previousembodiments may be interchanged to also use the characteristics of theP-type transistors transmitting stable high voltages and the N-typetransistors transmitting stable low voltages. In this case, the outputvoltage of the binary switch tree may be the second voltage VH.

As an example, when the digital signal D9D8D7D6D5D4D3 is 0000000, theoutput first voltage VL is V0; when the digital signal D9D8D7D6D5D4D3 is0000001, the output first voltage VL is V1; and when the digital signalD9D8D7D6D5D4D3 is 1111111, the output first voltage VL is V127.

In the example of FIG. 2, the operation module 216 may include a firstoperation amplifier. The first operation amplifier may include a firstnon-inverting input terminal configured to receive the first voltage VL;a second non-inverting input terminal configured to receive the higherone of two adjacent reference voltages (e.g., V64); a first invertinginput terminal configured to receive the lower one of the two adjacentreference voltages (e.g., V63); a second inverting input terminalcoupled to the output terminal; and the output terminal configured tooutput the second voltage VH. As such, the first operation amplifier mayform an adder so as to generate the second voltage VH higher than thefirst voltage VL by an interval voltage according to two adjacentreference voltages of 128 reference voltages and the first voltage VL.According to this example, the adjacent voltage of the first voltage canbe obtained by only one multi-input operation amplifier, therebysimplifying the structure of the digital-to-analog conversion circuit.

In the example, V64 and V63 at the midpoint of the 128 referencevoltages are used as two adjacent reference voltages. It should be notedthat the embodiments of the present disclosure are not limited thereto.As another example, other adjacent reference voltages in the middlerange may also be used. As a further example, adjacent referencevoltages in other ranges may also be used.

In addition, in other embodiments using 128 reference voltages from highto low, the first operation amplifier in the previous embodiments may beconfigured to generate the first voltage VL lower than the secondvoltage VH by the interval voltage according to two adjacent referencevoltages and the second voltage VH.

FIG. 4 illustrates a circuit diagram of the operation module 216according to one embodiment of the present disclosure. As illustrated inFIG. 4, the first operation amplifier may use a rail to rail operationamplifier structure.

A first bias voltage Vb is input to the control electrodes of the firsttransistor M1 and the second transistor M2. The first electrodes of thefirst transistor M1 and the second transistor M2 are coupled to a highlevel signal terminal VDD, and the second electrodes of the firsttransistor M1 and the second transistor M2 are coupled to the firstelectrodes of the third transistor M3 and the fourth transistor M4 andthe first electrodes of the fifth transistor M5 and the sixth transistorM6, respectively. The transistors M1 and M2 may provide bias currentsfor the transistors M3-M6. The control electrode of the third transistorM3 is coupled to the second non-inverting input terminal, to which thereference voltage V64 is input, and the second electrode of the thirdtransistor M3 is input to a summing circuit. The control electrode ofthe fourth transistor M4 is coupled to the second inverting inputterminal, to which the reference voltage V63 is input, and the secondelectrode of the fourth transistor M4 is input to the summing circuit.The control electrode of the fifth transistor M5 is coupled to the firstnon-inverting input terminal, and the first voltage VL is input thereto,the second electrode of the fifth transistor M5 is coupled to the secondelectrode of the third transistor M3, and is input to the summingcircuit. The control electrode of the sixth transistor M6 is coupled tothe first inverting input terminal and the output terminal of thesumming circuit, the second electrode of the sixth transistor M6 iscoupled to the second electrode of the fourth transistor M4, and isinput to the summing circuit. Each of the above transistors M1-M6 is aP-type transistor. The output terminal of the summing circuit is theoutput terminal of the first operation amplifier and outputs the secondvoltage VH.

Similarly, a second bias voltage Vb1 is input to the control electrodesof the seventh transistor M7 and the eighth transistor M8. The firstelectrodes of the seventh transistor M7 and the eighth transistor M8 arecoupled to the ground terminal GND, and the second electrodes of theseventh transistor M7 and the eighth transistor M8 are coupled to thefirst electrodes of the ninth transistor M9 and the tenth transistor M10and the first electrodes of the eleventh transistor M11 and the twelfthtransistor M12, respectively. The transistors M7 and M8 may provide biascurrents for the transistors M9-M12. The control electrode of the ninthtransistor M9 is coupled to the second non-inverting input terminal, towhich the reference voltage V64 is input, and the second electrode ofthe ninth transistor M9 is input to the summing circuit. The controlelectrode of the tenth transistor M10 is coupled to the second invertinginput terminal, to which the reference voltage V63 is input, and thesecond electrode of the tenth transistor M10 is input to the summingcircuit. The control electrode of the eleventh transistor M11 is coupledto the first non-inverting input terminal, and the first voltage VL isinput thereto, the second electrode of the eleventh transistor M11 iscoupled to the second electrode of the ninth transistor M9, and is inputto the summing circuit. The control electrode of the twelfth transistorM12 is coupled to the first inverting input terminal and the outputterminal of the summing circuit, the second electrode of the twelfthtransistor M12 is coupled to the second electrode of the tenthtransistor M10, and is input to the summing circuit. Each of the abovetransistors M7-M12 is an N-type transistor. The summing circuit may usethe existing summing circuit, which will not be repeated here.

By using the above rail to rail operation amplifier structure, in theembodiment of the present disclosure, according to the characteristicsof the P-type transistor transmitting stable high voltages and N-typetransistor transmitting stable low voltages, P-type transistors are usedto transmit the high voltages, and N-type transistors are used totransmit the low voltages, so that the magnitude of the output voltageof the output terminal corresponds to the magnitude of the inputvoltage. According to the principle of the adder, it can be calculatedthat the voltage value of the second voltage VH is the sum of the firstvoltage VL and the voltage difference (i.e., the interval voltage)between the adjacent voltages, that is, VH=VL+V64−V63.

Thus, the multi-input operation amplifier is used to realize thefunction of the adder in order to generate the adjacent first voltage VLand second voltage VH for used in the subsequent seconddigital-to-analog converter, thereby greatly reducing the number ofswitches while reducing the chip area and production cost. Meanwhile,the rail to rail operation amplifier structure is used in connectionwith P-type transistors and N-type transistors, so that the outputvoltage may effectively follow the range of input voltage, to obtain acomplete and stable voltage transmission.

Similarly, in other embodiments using 128 reference voltages from highto low, the corresponding principle of the subtracter may be used, andthus it can be calculated that the voltage value of the first voltage VLmay be the difference between the second voltage VH and the voltagedifference (i.e., the interval voltage) of the adjacent voltages, thatis, VL=VH−V64+V63, thereby obtaining the first voltage VL.

In the example of FIG. 2, the second digital-to-analog converter 220 mayinclude three second voltage selection modules 222-1 to 222-3, each ofwhich is configured to select the first voltage VL or the second voltageVH according to a corresponding one of 3 low bits, and a weightedsumming module 224 configured to generate a third voltage correspondingto the 3 low bits as the weighted sum of the output voltages of thethree second voltage selection modules, and to generate the sum of thethird voltage and the first voltage.

In an example, the second voltage selection modules may be transmissiongates. Input terminals of the respective transmission gates may beprovided with the first voltage VL and the second voltage VHrespectively, control terminals of the transmission gates may beprovided with the 3-bit digital signal D2, D1 and D0 in low bits ascontrol signals of the transmission gates, and output terminals of therespective transmission gates may be accordingly coupled to first tothird non-inverting input terminals Vin1, Vin2 and Vin3 of the weightedsumming module. For example, when the control signal D2 of thetransmission gate 222-1 is 0, the transmission gate 222-1 may output thefirst voltage VL to the first non-inverting input terminal Vin1; andwhen D2 is 1, the transmission gate 222-1 may output the second voltageVH to the first non-inverting input terminal Vin1. Additionally, VL maybe directly coupled to the fourth non-inverting input terminal Vin4 ofthe weighted summing module.

In an example, the weighted summing module 224 may be a second operationamplifier including the first to third non-inverting input terminalsVin1-Vin3 configured to receive the output voltages of the three secondvoltage selection modules, the fourth non-inverting input terminal Vin4configured to receive the first voltage VL, the inverting input terminalcoupled to the output terminal, and the output terminal configured tooutput the sum of the third voltage and the first voltage. As anexample, the second operation amplifier may use multi-input buffer.

The ratio of the weights of the input terminals of the weighted summingmodule is 4:2:1:1. Since the ratio of the weights of the first to thirdnon-inverting input terminals is 4:2:1, the binary number represented bythe 3-bit digital signal D2D1D0 in low bits can be converted into thecorresponding analog signal. Since the first voltage VL is also input tothe weighted summing module at the same time, the sum of the firstvoltage VL corresponding to the 7-bit digital signal and the thirdvoltage corresponding to the 3-bit digital signal can be obtaineddirectly. As an example, the value of the aspect ratio W/L of each inputtransistor in the second operation amplifier may be set to 4:2:1:1. Foranother example, other existing operation amplifiers with weightedsumming function may also be used. As such, the sum of the third voltageand the first voltage can be controlled between the first voltage VL and1/8VL+7/8VH (that is, VL+7/8Δ, wherein Δ is the difference between VHand VL, i.e., the interval voltage) at equal intervals. Specificinput/output configuration of the second digital-to-analog converter maybe shown in Table 1 below.

TABLE 1 D2D1D0 Vin1 Vin2 Vin3 Vin4 Vout 000 VL VL VL VL VL 001 VL VL VHVL 7/8VL + 1/8VH 010 VL VH VL VL 6/8VL + 2/8VH 011 VL VH VH VL 5/8VL +3/8VH 100 VH VL VL VL 4/8VL + 4/8VH 101 VH VL VH VL 3/8VL + 5/8VH 110 VHVH VL VL 2/8VL + 6/8VH 111 VH VH VH VL 1/8VL + 7/8VH

In the above example, the second digital-to-analog converter consists ofthe transmission gate and the operation amplifier (such as a buffer).When the number of bits of the digital signal corresponding to thesecond digital-to-analog converter is greater, the number of input pairswill be greater. However, the voltage difference in the multi-inputbuffer is linear, which may not completely coincide with the grayscalecurve of the image signal. And, if the voltage difference between theinput voltages is too high, there will be a certain gap between theoutput value and the internal difference value. Thus, in the aboveexample where a multi-input buffer is used, the n low bits are typicallytwo or three bits. However, the embodiments of the present disclosureare not limited to the above example. As another example, the seconddigital-to-analog converter may also use the resistor string typedigital-to-analog converter. In this case, the value of n is not limitedto 2 or 3.

In this way, 127 resistors and 254 switches are used in the aboveembodiments. As compared with the conventional 10-bit digital-to-analogconversion circuit using the transmission gate as the switching element,the number of switches can be reduced significantly, and the switch areacan be reduced by 8 times. As the switch area usually accounts for about50% of the chip area, the chip area can be reduced by 3-4 times.

The digital-to-analog conversion circuit according to the embodiments ofthe present disclosure has been described above as an illustrativeexample in which m is 7 and n is 3. Obviously, m and n may be othersuitable values as needed. For example, a 9-bit first digital-to-analogconverter and a 3-bit second digital-to-analog converter may be used toobtain a 12-bit digital-to-analog conversion circuit.

As an alternative to the above embodiments, a global resistor switchtree structure may also be used. In this way, good linearity and smallerglitches can be ensured. In this case, for a 10-bit digital-to-analogconversion circuit, m=10 and n=0. This 10-bit global resistor switchtree consists of 1023 resistors connected in series with equalresistances to form 1024 reference voltages, and uses 2046 switches toselect the output voltage signal corresponding to the 10-bit digitalsignal. In this alternative embodiment, the 2046 switches use a singletransistor as in the previous embodiments, with the P-type transistorfor the high voltage range, and the N-type transistor for the lowvoltage range. In this way, it is still possible to effectively reducethe number of switches as compared with the conventional 10-bitdigital-to-analog conversion circuit using the transmission gate as theswitching element.

II. Source Driver

FIG. 6 illustrates a source driver 610 according to an embodiment of thepresent disclosure, which includes the digital-to-analog conversioncircuit as described in Section I above. The rest of the source drivermay be the same as an existing source driver, which will not be repeatedhere.

III. Display Apparatus

FIG. 6 illustrates a display apparatus 620 according to an embodiment ofthe present disclosure, which includes the source driver 610 asdescribed in Section II above. In particular, the source driver of thedisplay apparatus may include the digital-to-analog conversion circuitas described in Section I above. The display apparatus may be, forexample, an OLED display apparatus (e.g., AMOLED display apparatus), aliquid crystal display apparatus, or the like.

IV. Digital-To-Analog Conversion Method

FIG. 5 illustrates a flowchart of a method for digital-to-analogconversion according to an embodiment of the present disclosure. Thedigital-to-analog conversion method may be used for digital-to-analogconversion in the display apparatus (e.g., its source driver).

As illustrated in FIG. 5, in step S510, the first digital-to-analogconversion corresponding to m high bits of the (m+n)-bit digital signalmay be performed by the first digital-to-analog converter as describedin Section I. In particular, in step S512, 2^(m) reference voltages atequal intervals in voltage may be generated. This may be performed bythe voltage division module as in Section I. In step S514, the firstvoltage corresponding to the m bits may be selected from the 2^(m)reference voltages. This may be performed by the first voltage selectionmodule as in Section I. In step S516, the second voltage higher than thefirst voltage by the interval in voltage may be generated according totwo adjacent reference voltages of the 2^(m) reference voltages and thefirst voltage. This may be performed by the operation module as inSection I.

In step S520, the second digital-to-analog conversion corresponding to nlow bits may be performed by the second digital-to-analog converter asdescribed in Section I. In particular, step S520 may include step S522in which the third voltage corresponding to the n bits may be generatedby using the first voltage and the second voltage as reference voltages,and the sum of the third voltage and the first voltage may be generated.The details of steps S510 and S520 have been described in detail inSection I, and will not be repeated here.

The units or modules described herein may be implemented as acombination of a processor and a memory, where the processor executesthe program stored in the memory to implement the function of thecorresponding unit or module. The units or modules described herein mayalso be implemented in complete hardware implementation, includingapplication specific integrated circuits (ASICs), field programmablegate arrays (FPGAs), and the like.

The above descriptions are merely exemplary embodiments of the presentdisclosure, and are not intended to limit the protection scope of thepresent disclosure. The protection scope of the disclosure is determinedby the appended claims.

We claim:
 1. A digital-to-analog conversion circuit comprising: a firstdigital-to-analog converter comprising: a voltage division moduleconfigured to generate 2^(m) reference voltages at equal intervals involtage, where m is an integer greater than 0; a first voltage selectionmodule configured to select, from the 2^(m) reference voltages, a firstvoltage corresponding to the m high bits of an input signal; and anoperation module configured to generate a second voltage, which ishigher than the first voltage by the interval in voltage, based on twoadjacent reference voltages of the 2^(m) reference voltages and thefirst voltage; and a second digital-to-analog converter configured togenerate a third voltage corresponding ton low bits of the input signalby using the first voltage and the second voltage as reference voltageswhere n is an integer greater than 0, and to generate the sum of thethird voltage and the first voltage.
 2. The digital-to-analog conversioncircuit according to claim 1, wherein the operation module comprises afirst operation amplifier comprising: a first non-inverting inputterminal configured to receive the first voltage; a second non-invertinginput terminal configured to receive the higher one of the two adjacentreference voltages; a first inverting input terminal configured toreceive the lower one of the two adjacent reference voltages; a secondinverting input terminal coupled to the output terminal; and the outputterminal configured to output the second voltage.
 3. Thedigital-to-analog conversion circuit according to claim 1, wherein thetwo adjacent reference voltages are the middle ones of the 2^(m)reference voltages.
 4. The digital-to-analog conversion circuitaccording to claim 1, wherein the first voltage selection modulecomprises: a binary switch tree comprising m layers of switches, thefirst layer comprising two switch branches coupled to the outputterminal, the m^(th) layer comprising 2^(m) switch branches each coupledto one of the 2^(m) reference voltages, respectively, and each of the mlayers being controlled by a corresponding, one of the m bits, so thatthe output terminal outputs the first voltage; wherein switchingelements of the switch branches corresponding to the reference voltagesof the 2^(m) reference voltages higher than or equal to a predeterminedvoltage are P-type transistors, and switching elements of the switchbranches corresponding to the reference voltages of the 2^(m) referencevoltages lower than the predetermined voltage are N-type transistors. 5.The digital-to-analog conversion circuit according to claim 4, whereinthe predetermined voltage is the middle one of the 2^(m) referencevoltages.
 6. The digital-to-analog conversion circuit according to claim1, wherein the second digital-to-analog converter comprises: n secondvoltage selection modules each configured to select the first voltage orthe second voltage based on a corresponding one of the n bits; and aweighted summing module configured to generate the third voltage as aweighted sum of the output voltages of the n second voltage selectionmodules and to generate the sum of the third voltage and the firstvoltage.
 7. The digital-to-analog conversion circuit according to claim6, wherein: the second voltage selection modules are transmission gates;the weighted summing module comprises a second operation amplifiercomprising: 1^(st) to n^(th) non-inverting input terminals configured toreceive the output voltages of the n second voltage selection modules; a(n+1)^(th) non-inverting input terminal configured to receive the firstvoltage; an inverting input terminal coupled to the output terminal; andthe output terminal configured to output the sum of the third voltageand the first voltage.
 8. The digital-to-analog conversion circuitaccording to claim 1, wherein the voltage division module is a voltagedivision module having a resistor string type.
 9. A source drivercomprising the digital-to-analog conversion circuit according toclaim
 1. 10. A display apparatus comprising the source driver accordingto claim
 9. 11. A method for digital-to-analog conversion, the methodcomprising: performing a first digtal-to-analog conversion comprisinggenerating 2^(m) reference voltages at equal intervals in voltage, wherem is an integer greater than 0; selecting from the 2^(m) referencevoltages, a first corresponding to m high bits of an input signal; andgenerating a second voltage which is higher than the first voltage bythe interval in voltage based on two adjacent reference voltages of the2^(m) reference voltages and the first voltage; and performing a seconddigital-to-analog conversion comprising: generating a third voltagecorresponding to n low bits of the input signal by using the firstvoltage and the second voltage as reference voltages, where n is aninteger greater than 0; and generating the sum of the third voltage andthe first voltage.
 12. The method for digital-to-analog conversionaccording to claim 11, wherein the first voltage is selected by using abinary switch tree, and the binary switch tree comprises m layers ofswitches, the first layer comprising two switch branches coupled to theoutput terminal, the m^(th) layer comprising 2^(m) switch branches eachcoupled to one of the 2^(m) reference voltages, respectively, and eachof the m layers being controlled by a corresponding one of them bits, sothat the output terminal outputs the first voltage; wherein switchingelements of the switch branches corresponding to the reference voltagesof the 2^(m) reference voltages higher than or equal to a predeterminedvoltage are P-type transistors, and switching elements of the switchbranches corresponding to the reference voltages of the 2^(m) referencevoltages lower than the predetermined voltage are N-type transistors.